1. Technical Field
The present invention relates to a metal oxide semiconductor field-effect transistor (MOSFET) for DC-DC converter application, and more specifically, to a metal oxide semiconductor field-effect transistor integrating a bypass capacitor for DC-DC converter application.
2. Description of the Related Art
In the DC-DC converter, a capacitor is often used as a filter capacitor as shown in FIG. 1A, wherein the source S1 of the N-type high side MOSFET1 connects the drain D2 of the N-type low side MOSFET 2, while a capacitor 3 is connected between the drain D1 of the high side MOSFET1 and the source S2 of the low side MOSFET 2. Discrete capacitors have been used for their low cost and high performance. In current trend of miniaturization of electronic components for handheld electronic device application, it is desirable to incorporate a capacitor into a semiconductor chip package. One solution is integrating a capacitor in the DC-DC converter package, in which a separate capacitor and the metal oxide semiconductor field-effect transistors (MOSFET) are simultaneously co-packaged in a package structure through epoxy resin. As the structure shown in the schematic diagram of FIG. 1B, the low side MOSFET and the high side MOSFET stacking one on another with a capacitor sandwiched there between corresponding to the circuit diagram shown in FIG. 1A, wherein the semiconductor chip 10 in FIG. 1B constitutes the high side MOSFET1 in FIG. 1A, while the semiconductor chip 20 in FIG. 1B constitutes the low side MOSFET2 in FIG. 1A. The die size of the high side semiconductor chip 10 is smaller than that of the low side semiconductor chip 20 with the semiconductor chip 10 stacking on the semiconductor chip 20 while the semiconductor chip 20 sticking on metal lead frame 30. The top surface of low side MOSFET chip 20 comprises a low side source metal layer 22 having a low side source bonding area 22a, a dielectric layer (not shown) covering substantially the whole low side metal layer 22 except the source bonding area 22a. A high side drain metal layer 13 is deposited over the dielectric layer on top of the low side source metal layer 22 separated from the source metal layer 22 by the dielectric layer.
Wherein, a high side gate bonding region 11 of the semiconductor chip 10 is connected to a high side gate pin 11b through a bonding wire 11a; a high side source bonding region 12 of the semiconductor chip 10 is connected to the lead frame 30 through bonding wires 12a; a high side drain (not shown in the figure) at the bottom of the semiconductor chip 10 is stuck onto the high side drain metal layer 13 via conductive silver paste (Epoxy), and meanwhile the high side drain metal layer 13 is connected to high side drain pin 13b through bonding wire 13a. The high side drain metal layer 13 has larger sizes than the semiconductor chip 10.
Wherein, a low side gate bonding region 21 of the semiconductor chip 20 is connected to a low side gate pin 21b via a gate bonding wire 21a; the source metal layer 22 of the semiconductor chip 20 is provided with a source bonding region 22a for connecting to a source pin 22c via bonding wires 22b; a low side drain (not shown in the figure) at the bottom of the semiconductor chip 20 is stuck onto the lead frame 30 via conductive silver paste (Epoxy electrically connected with the high side source bonding region 12 of the semiconductor chip 10 through bonding wires 12a. 
Wherein, the tri-layer structure of the dielectric layer (not shown in the figure) between the high side drain metal layer 13 of the semiconductor chip 10 and the low side source metal layer 22 of the semiconductor chip 20 provides a capacitor. However, such a capacitor usually does not provide enough capacitance for many applications.